The present invention relates to silicon on insulator integrated circuits.
A common problem in silicon on insulator devices is passivation of the sidewalls. Since the sidewalls are not (100) silicon, they will often have an inherently somewhat lower threshold voltage than the plane in which the primary active devices are constructed, and thus passivation of the sidewalls is particularly difficult.
Moreover, silicon on insulator circuits are particularly attractive for applications which must be extremely resistant to single event upset. For such applications, the fixed charge density of the dielectric interface cannot be reliably expected to stay at the as-manufactured level, and therefore it is particularly desirable that the parasitic transistors along the sidewalls of the mesa be very far from inversion, i.e. very far away from their threshold voltages.
Heavier channel stop doping on the sidewalls of the mesas would obviously help to accomplish this, but to date there has been no fully satisfactory way to achieve this. Since these sidewall regions are nearly vertical, they are difficult to hit with implantation steps. Moreover, there has heretofore been no convenient self-aligned sequence of steps to leave the sidewall regions exposed.
The most popular way to form the sidewall channel stops has been to introduce a heavy doping, patterned by the mesa mask, and drive that dopant to achieve a substantial lateral diffusion before the mesa etch is performed. However, this has the disadvantage of requiring long furnace times early in the process, and also results in a device where the threshold voltage of the parasitic sidewall transistors in the finished device is critically dependent on the time and temperature of this furnace step. Moreover, due to the concentration gradient implied by the diffusion equations, such lateral diffusion techniques will always produce a net concentration in the sidewalls of the mesa which is lower than the original maximum net concentration in the silicon between mesas.
That is, devices formed using the present invention will tend to not only have a region wherein the dopant concentration of the sidewall channel stop tails off in a manner indicated by the diffusion equations (as will the devices made by previously known methods), but will also have a surface region where the concentration of impurities is reasonably constant.
Thus, the present invention provides major advantages in device characteristics at the cost of only minor additions to processing complexity. That is, the present invention provides silicon on insulator IGFET integrated circuit devices which, for a given effective channel length and dielectric composition, are substantially more resistant to turn on of the parasitic sidewall device than devices made by previously known methods.
The present invention also provides silicon on insulator IGFET integrated circuit devices which can remain functional even when the fixed charge density of the dielectric interface increases greatly from the as-manufactured level.
The present invention also provides silicon on insulator IGFET integrated circuit devices which can remain functional after withstanding a substantially higher total dose of ionizing radiation than silicon on insulator IGFET integrated circuit devices of the prior art.
further advantage of the present invention is that leakage current can be significantly reduced. That is, since the threshold voltage of the parasitic transistor is substantially increased, this parasitic device in its normal state will be farther away from its threshold voltage, and therefore its subthreshold current will be less.
Thus, the present invention provides integrated circuits with substantially improved radiation hardness.
The present invention also advantageously provides integrated circuits with improved radiation hardness at no sacrifice in density.
The present invention also advantageously provides integrated circuits with improved radiation hardness and reduced power consumption.
The advantage of reduced leakage currents is particularly important in CMOS integrated circuits. Thus, the present invention is especially advantageous for CMOS silicon on insulator and CMOS silicon on sapphire integrated circuits.
Thus, the present invention provides silicon on insulator IGFET integrated circuit devices which, for a given effective channel length and dielectric composition, have substantially lower leakage current (and hence lower average power consumption) than will devices made by previously known methods.
In particular, the present invention provides CMOS silicon on insulator IGFET integrated circuit devices which, for a given effective channel length and dielectric composition, have substantially lower (leakage current (and hence lower average power consumption) than will devices made by previously known methods.
The present invention also provides silicon on insulator IGFET integrated circuit devices which have substantially lower leakage current (and hence lower average power consumption) than comparable prior art devices under conditions where the fixed charge density of the dielectric interface increases greatly from the as-manufactured level.
In particular, the present invention provides CMOS silicon on insulator integrated circuits which have substantially lower leakage current (and hence lower average power consumption) than comparable prior art devices under conditions where the fixed charge density of the dielectric interface increases greatly from the as-manufactured level.
The present invention also provides silicon on insulator IGFET integrated circuit devices which have substantially lower leakage current (and hence lower average power consumption) than comparable prior art devices after withstanding a substantially higher total dose of ionizing radiations.
In particular, the present invention provides CMOS silicon on insulator integrated circuits which have substantially lower leakage current (and hence lower average power consumption) than comparable prior art devices after withstanding a substantially higher total dose of ionizing radiations.
The present invention can also be adapted for use with semiconductor materials other than silicon. In particular, the present invention can also be applied to semiconductors closely related to silicon, such as Si.sub.x Ge.sub.(1-x), or Si/Si.sub.x Ge.sub.(1-x) graded-composition structures, or Si/Si.sub.x C.sub.(1--x) graded-composition structures, or Si/Si.sub.x C.sub.(1-x) /Si.sub.x Ge.sub.(1-x) graded-composition structures. The present invention can also be applied to self-aligned isolation implantation in III-V devices. Particularly in III-V semiconductors with relatively small bandgaps (e.g. 1.5 eV or less), implantation of dopants to avoid inversion at a dielectric interface (with consequent turn-on of a parasitic device) may be useful. Alternatively, in many III-V devices unannealed implantation damage is used for isolation (due to the effects of lattice damage), and the present invention may also be used to provide a narrow region of isolation of this type next to the edge of a mesa or trench.
The present invention can also (somewhat less preferably) be adapted to apply to improve isolation characteristics of trench-isolated bulk devices generally. That is, etching a trench and providing an insulating material to stop leakage current across the trench is not the end of isolation requirements: it is also necessary to control parasitic and leakage currents which might run laterally in the semiconductor material along the faces of the trench. By using a mask for an isolation implant which is differentiated from the trench etch mask by a self-aligned sidewall filament, the present invention provides a self-aligned isolation region at the faces of the isolation trench, down to a depth determined by the implant energy and diffusion length.
The present invention can also be adapted to avoid sidewall leakage and inversion problems in semiconductor or insulator integrated circuits using other types of active devices, such as bipolar or MESFET transistors, or others: the advantages of the present invention are generally applicable.
According to the present invention there is provided: A semiconductor-on-insulator device fabricated by the steps of: providing a substrate having at a surface thereof a layer of monocrystalline semiconductor material overlying a layer of an insulator; providing a patterned masking layer over said monocrystalline semiconductor layer, said masking layer being patterned to cover predetermined portions of said semiconductor layer where active devices are to be formed; implanting a channel stop dopant substantially into portions of said semiconductor material which are not covered by said masking layer; forming sidewall filaments on said patterned masking layer, so that said patterned masking layer with said filaments covers a larger fraction of said semiconductor layer than was covered by said masking layer alone, but does not cover all of said semiconductor layer; etching away said semiconductor material except where substantially covered by said masking layer and/or said sidewall filaments on said masking layer, said etching step leaving semiconductor mesas separated by areas of said insulators; providing a dielectric covering at least some portions of said semiconductor mesas; and forming a patterned thin film of conductive material, said patterned thin film of a conductive material providing gates of field effect transistors having channel regions in said mesa. Bipolar transistors may be fabricated in some of the semiconductor mesas.
According to the present invention there is also provided: A process for fabricating a semiconductor-on-insulator integrated circuit structure, comprising the steps of: providing a substrate having at a surface thereof a layer of monocrystalline semiconductor material overlying a layer of an insulator; providing a patterned masking layer over said monocrystalline semiconductor layer, said masking layer being patterned to cover predetermined portions of said semiconductor layer where active devices are to be formed; implanting a dopant substantially into at least some of the portions of said semiconductor material which are not covered by said masking layer; forming sidewall filaments on said patterned masking layer, so that said patterned masking layer with said filaments covers a larger fraction of said semiconductor layer than was covered by said masking layer alone, but does not cover all of said semiconductor layer; and fabricating active devices in said mesas.
According to the present invention there is also provided: A process for fabricating a semiconductor-on-insulator device, comprising the steps of: providing a substrate having at a surface thereof a layer of monocrystalline semiconductor material overlying a layer of an insulator; providing a patterned masking layer over said monocrystalline semiconductor layer, said masking layer being patterned to cover predetermined portions of said semiconductor layer where active devices are to be formed; implanting a p-type channel stop dopant into some portions of said semiconductor material which are not covered by said masking layer; forming sidewall filaments on said patterned masking layer, so that said patterned masking layer with said filaments covers a larger fraction of said semiconductor layer than was covered by said masking layer alone, but does not cover all of said semiconductor layer; etching away said semiconductor material except where substantially covered by said masking layer and/or said sidewall filaments on said masking layer, said etching step leaving semiconductor mesas separated by areas of said insulator; providing a dielectric covering at least some portions of said semiconductor mesas; and forming a patterned thin film of conductive material, said patterned thin film of a conductive material providing gates of n-channel field effect transistors having channel regions in ones of said mesas which include an admixture of dopant atoms introduced by said channel stop implanting step around the periphery thereof, and also of p-channel field effect transistors having channel regions in others of said mesas.
According to the present invention there is also provided: A process for fabricating a semiconductor-on-insulator device, comprising the steps of: providing a substrate having at a surface thereof a layer of monocrystalline semiconductor material overlying a layer of an insulator; providing a patterned masking layer over said monocrystalline semiconductor layer, said masking layer being patterned to cover predetermined portions of said semiconductor layer where active devices are to be formed; implanting a channel stop dopant substantially into portions of said semiconductor material which are not covered by said masking layer; forming sidewall filaments on said patterned masking layer, so that said patterned masking layer with said filaments covers a larger fraction of said semiconductor layer than was covered by said masking layer alone, but does not cover all of said semiconductor layer; etching away said semiconductor material except where substantially covered by said masking layer and/or sidewall filaments on said masking layer, said etching step leaving semiconductor mesas separated by areas of said insulator; providing a dielectric covering at least some portions of said semiconductor mesas; and forming a patterned a thin film of conductive material, said patterned thin film of a conductive material providing gates of field effect transistors having channel regions in said mesa.